Direct Connection To The Philips Pr31500/Pr31700; Hardware Description - Epson S1D13505F00A Technical Manual

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4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR

• Address input AB17 should be connected to the PR31500/PR31700 signal /CARDIOWR. Either

AB17 or the WE0# input must be asserted for a write operation to take place.

• Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to V

not used in this interface mode.

• Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the PR31500/PR31700

address and data bus, respectively. MD4 must be set to select the proper endian mode on reset (see

"S1D13505 Conﬁguration" on page 14). Because of the PR31500/PR31700 data bus naming

convention and endian mode, S1D13505 DB[15:8] must be connected to PR31500/PR31700

D[23:16], and S1D13505 DB[7:0] must be connected to PR31500/PR31700 D[31:24].

• Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700 signals /

CARDxCSH and /CARDxCSL respectively for byte steering.

• Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the AB18

input (/CARDIORD) must be asserted for a read operation to take place.

• Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or the AB17

input (/CARDIOWR) must be asserted for a write operation to take place.

• WAIT# is a signal output from the S1D13505 that indicates the host CPU must wait until data is

ready (read cycle) or accepted (write cycle) on the host bus. Since the host CPU accesses to the

S1D13505 may occur asynchronously to the display update, it is possible that contention may

occur in accessing the S1D13505 internal registers and/or display buffer. The WAIT# line resolves

these contentions by forcing the host to wait until the resource arbitration is complete.

4.4 Direct Connection to the Philips PR31500/PR31700

The S1D13505 was speciﬁcally designed to support the Philips MIPS PR31500/PR31700 processor.

When conﬁgured, the S1D13505 will utilize one of the PC Card slots supported by the processor.

Hardware Description

In this example implementation, the S1D13505 occupies one PC Card slot and resides in the

Attribute and IO address range. The processor provides address bits A[12:0], with A[23:13] being

multiplexed and available on the falling edge of ALE. Peripherals requiring more than 8K bytes of

address space would require an external latch for these multiplexed bits. However, the S1D13505

has an internal latch speciﬁcally designed for this processor making additional logic unnecessary. To

further reduce the need for external components, the S1D13505 has an optional BUSCLK divide-

by-2 feature, allowing the high speed DCLKOUT from the processor to be directly connected to the

BUSCLK input of the S1D13505. An optional external oscillator may be used for BUSCLK since

the S1D13505 will accept host bus control signals asynchronously with respect to BUSCLK.

The following diagram shows a typical implementation of the interface.

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Direct Connection To The Philips Pr31500/Pr31700; Hardware Description - Epson S1D13505F00A Technical Manual

4.4 Direct Connection to the Philips PR31500/PR31700

Hardware Description

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