Direct Connection To The Philips Pr31500/Pr31700; Hardware Description - Epson S1D13504 Technical Manual

Epson Research and Development
Vancouver Design Center

4 Direct Connection to the Philips PR31500/PR31700

4.1 Hardware Description

PR31500/PR31700
/RD
/WE
/CARD1CSL
/CARD1CSH
ALE
A[12:0]
D[31:24]
D[23:16]
/CARD1WAIT
ENDIAN
DCLKOUT
Note:
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection
Note
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/02
The S1D13504 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct
connection implementation, the S1D13504 occupies PC Card slot #1 of the
PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it
can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct
connection implementation makes use of the Generic MPU host bus interface capability of
the S1D13504.
The following diagram demonstrates a typical implementation of the PR31500/PR31700 to
S1D13504 interface.
Latch
V
DD 15K pull-up
Clock divider
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
+3.3V
A23
System RESET
A[20:13]
See text
...or...
Oscillator
Page 11
S1D13504
IO V , CORE V
DD DD
RD0#
RD1#
WE0#
WE1#
CS#
M/R#
RESET#
AB[20:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
BUSCLK
CLKI
S1D13504
X19A-G-005-08