WAGO 750-830 Manual page 67

3.1.6.2.2 Example of Addressing
Two digital input modules (2 DI), two digital output modules (2 DO) and two
analog input modules (2 AI) and two analog output modules (2AO) are con-
nected to one controller. The final element is an end module that is not taken
into account for addressing.
Tab. 3-6: Example of addressing
Count
Se-
quence
1.
2.
3.
4.
-
Refer to the technical data for the specific modules for the data width. The
analog input modules (AI) are mapped first in the process image. Analog
modules are processed word-by-word (W). Module 467 occupies 2 words here
(1 word = 16 Bit); i.e., the first word %IW0 and the second word %IW1 in
the memory image. Note here that counting begins at "0".
The digital inputs (DI) are taken into account after this. These occupy 2 bits.
Two complete words have been previously counted (Word 0 and 1). Now,
counting is continued from Word 2 and 2 bits are added (Bit 0 and Bit 1).
Words and bits are each separated by a decimal point. Hardware addresses are
then %IX2.0 and %IX2.1.
The two analog output modules 750-550 (AO) are then processed. Each of
these modules occupies 1 word; i.e., together they occupy 2 words. Counting
for the output process image begins anew at "0". The hardware output ad-
dresses are then %QW0 and %QW1.
Now the digital outputs (DO) are dealt with. These occupy 2 bits. Two com-
plete words have been previously counted (Word 0 and 1). Now, counting is
continued from Word 2 and 2 bits are added (Bit 0 and Bit 1). The hardware
addresses are then %QX2.0 and %QX2.1.
Note
Changing or adding of digital, analog or complex modules (DALI, EnOcean,
etc.) may result in a new process image being generated. The process data ad-
dresses would then also be changed. Therefore, the process data of all previous
modules has to be taken into account when modules are added.
WAGO-I/O-SYSTEM 750
BACnet/IP Controller
Module Function
750-467 2 AI / 0-10 Volt
750-400 2 DI
750-550 2 AO / 0-10 Volt
750-501 2 DO
750-600 End module
BACnet/IP Controller 750-830
Data Exchange
Data Width Hardware Address
2 x 16 Bit %IW0 and %IW1
2 x 1 Bit %IX2.0 and %IX2.1
2 x 16 Bit %QW0 and %QW1
2 x 1 Bit %QX2.0 and %QX2.1
none -
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