Sample And Hold - Renesas M16C Series Hardware Manual

R8C/11 Group

14.3 Sample and Hold

If the SMP bit in the ADCON2 register is set to "1" (with sample-and-hold), the conversion speed per
pin is increased to 28
and-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function
before starting A/D conversion.
When performing the A/D conversion, charge the comparator capacitor inside the microcomputer.
Figure 14.6 shows the A/D conversion timing diagram.
Sample & Hold
disabled
Sample & Hold
enabled
Figure 14.6 A/D Conversion Timing Diagram
14.4 A/D conversion cycles
Figure 14.7 shows the A/D conversion cycles.
A/D conversion mode
Without sample & hold
Without sample & hold
With sample & hold
With sample & hold
Figure 14.7 A/D Conversion Cycles
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
cycles for 8-bit resolution or 33
ØAD
Conversion time at the 1st bit
Sampling time Comparison
4φ AD cycle
Conversion time at the 1st bit
Sampling time Comparison
4φ AD cycle
Conversion
time
49 φ AD
8 bits
59 φ AD
10 bits
28 φ AD
8 bits
33 φ AD
10 bits
page 132 of 204
14.3 Sample and Hold/14.4 A/D conversion cycles
ØAD
at the 2nd bit
Comparison
Sampling time
φ
time time
2.5 AD cycle
at the 2nd bit
Comparison Comparison
time time
* Repeat until conversion ends
Conversion time
at the 1st bit
Sampling Comparison
time time
4 φ AD 2.0 φ AD
4 φ AD 2.0 φ AD
4 φ AD 2.5 φ AD
4 φ AD 2.5 φ AD
cycles for 10-bit resolution. Sample-
Comparison
Sampling time
φ
time
2.5 AD cycle
* Repeat until conversion ends * Repeat until conversion ends
time
Conversion time at the End process
2nd bit and the follows
Sampling Comparison
End process
time time
2.5 φ AD 2.5 φ AD 8.0 φ AD
2.5 φ AD 2.5 φ AD 8.0 φ AD
0.0 φ AD 2.5 φ AD 4.0 φ AD
0.0 φ AD 2.5 φ AD 4.0 φ AD