Sample And Hold; A/D Conversion Cycles - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
17.3

Sample and Hold

When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases to 28φAD cycles for 8-bit resolution or 33φAD cycles for 10-bit resolution. The sample and hold
function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold
circuit is to be used or not.
When performing A/D conversion, charge the comparator capacitor in the MCU during the sampling time.
Figure 17.6 shows a Timing Diagram of A/D Conversion.
Sample and Hold
disabled
Sample and Hold
enabled
Figure 17.6 Timing Diagram of A/D Conversion
17.4

A/D Conversion Cycles

Figure 17.7 shows the A/D Conversion Cycles.
A/D Conversion Mode
Without sample and hold
Without sample and hold
With sample and hold
With sample and hold
Figure 17.7 A/D Conversion Cycles
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
Conversion time of 1st bit
Comparison
Sampling time
4ø AD cycles
time
Conversion time of 1st bit
Comparison
Sampling time
4ø AD cycles
time
Conversion time of 1st bit
Conversion Sampling
Time
8 bits
49φAD
10 bits
59φAD
8 bits 28φAD
33φAD
10 bits
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2nd bit
Comparison
Sampling time
2.5ø AD cycles
time
2nd bit
Comparison Comparison
time time
* Repeat until conversion ends
Conversion time 2nd and
Comparison Sampling
Time Time
4φAD 2.0φAD 2.5φAD
4φAD 2.0φAD 2.5φAD
4φAD 2.5φAD 0.0φAD
4φAD 2.5φAD 0.0φAD
17. A/D Converter
Comparison
Sampling time
2.5ø AD cycles
time
* Repeat until conversion ends
Comparison
time
End of
following bits processing
Comparison
Time Time Processing
2.5φAD 8.0φAD
2.5φAD 8.0φAD
2.5φAD 4.0φAD
2.5φAD 4.0φAD
End