Freescale Semiconductor Symphony DSP56724 Reference Manual page 81

DSP56724 External Pins
Mode MODD1 MODC1
OMR:MD OMR:MC
0 0 0
1 0 0
2 0 0
3 0 0
4 0 1
5 0 1
6 0 1
7 0 1
8 1 0
9 1 0
A 1 0
B 1 0
C 1 1
D 1 1
E 1 1
F 1 1
Mode Name
Mode 0 Boot via SHI (SPI)
Mode 1 Boot via SHI
2
(I C Filter)
Mode 2 Jump to PROM (SPI)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 5-6. Core-1 Operating Modes in DSP56724
MODB1 MODA1 Reset Vector
OMR:MB OMR:MA
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Table 5-7. DSP56724 Core-0/Core-1 Boot Modes
In Mode 0, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI
operates in the SPI slave mode, with 24-bit word width.
The bootstrap code expects to read a single 24-bit word specifying the number of program
words, another 24-bit word specifying the address to start loading the program words, and
then a 24-bit word for each program word to be loaded.
The program words will be stored in contiguous PRAM memory locations starting at the
specified starting address. After reading the program words, program execution starts from
the same address where loading started.
Mode 1 boot mode uses the same operation as Mode 0
the SHI interface operates in the I
enabled.
The DSP starts fetching instructions from the starting address of the on-chip Program
ROM. SHI operates in SPI slave mode.
$FFFFFE Boot via SHI (SPI)
Boot via SHI (I2C Filter)
Jump to PROM (SPI)
Jump to PROM (I2C Filter)
Boot via Core-0
Boot via SHI Master (SPI-EEPROM)
Boot via SHI Master (I2C-EEPROM)
Boot via GPIO Master (SPI-EEPROM)
PE6/PE7/PE8/PE9
Boot via External Memory word-wide.
Not available in DSP56725 packages.
Boot via External Memory byte-wide.
Not available in DSP56725 packages.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
2 C slave mode, with HCKFR set to 1 and the 100 ns filter
Core Configuration
Description
(Boot via SHI (SPI)),
except that
5-7