Freescale Semiconductor Symphony DSP56724 Reference Manual page 234

Inter-Core Communication (ICC)
13.2.2.11 ICPR1 (ICC Poll Register 1)
The ICPR1 polling register is shown in
I
Address Y:FFFFD1
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–0 Poll Data
13.2.2.12 ICPR2 (ICC Poll Register 2)
The ICPR2 polling register is shown in
Address Y:FFFFD0
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–0 Poll Data
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
13-12
Figure
21 20
0 0 0
9 8
0 0 0
Figure 13-13. ICC_ICPR1 Polling Register
Table 13-13. CPR1 Field Descriptions
24-bit Poll data from the other core. Read-Only.
Figure
21 20
0 0 0
9 8
0 0 0
Figure 13-14. ICPR2 Polling Register
Table 13-14. CPR2 Field Descriptions
The DSP Core writes this register to transfer poll data to the other core. The data can be read out by
the other core by polling its own ICPR1 register.
13-13.
19 18 17
Data
0 0 0
7 6 5
Data
0 0 0
Description
13-14.
19 18 17
Data
0 0 0
7 6 5
Data
0 0 0
Description
Access: User Read
16 15 14
0 0 0
4 3 2
0 0 0
Access: User Read/Write
16 15 14
0 0 0
4 3 2
0 0 0
Freescale Semiconductor
13 12
0 0
1 0
0 0
13 12
0 0
1 0
0 0