Memory Map - Freescale Semiconductor Symphony DSP56724 Reference Manual

S/PDIF—Sony/Philips Digital Interface
18.1.3

Memory Map

Address Access
X:$FFFF60 R/W S/PDIFConfig (SCR)
X:$FFFF61 R/W CDTEXT_Control (SRCD)
X:$FFFF62 R/W PhaseConfig (SRPC)
X:$FFFF63 R/W InterruptEn (SIE)
X:$FFFF64 R InterruptStat/Clear (SIS/SIC)
-Stat
W
-Clear
X:$FFFF65 R SPDIFRcvLeft (SRL)
X:$FFFF66 R SPDIFRcvRight (SRR)
X:$FFFF67 R SPDIFRcvCChannel_h
(SRCSH)
X:$FFFF68 R SPDIFRcvCChannel_l (SRCSL) S/PDIF Receive C channel, bits [23:0]
X:$FFFF69 R UchannelRcv (SQU)
X:$FFFF6A R QchannelRcv (SRQ)
X:$FFFF6B W SPDIFTxLeft (STL)
X:$FFFF6C W SPDIFTxRight (STR)
X:$FFFF6D R/W SPDIFTxCChannelCons_h
(STCSCH)
X:$FFFF6E R/W SPDIFTxCChannelCons_l
(STCSCL)
X:$FFFF6F R/W SPDIFTxCChannelProf_h
(STCSPH)
X:$FFFF70 R/W SPDIFTxCChannelProf_l
(STCSPL)
X:$FFFF71 R FreqMeas (SRFM)
X:$FFFF74 R/W SPDIFTxClk (STC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
18-4
Table 18-2. S/PDIF Memory Map
Register Name
S/PDIF Configuration Register
CDText Configuration Register
FreqMeas Configuration Register
Interrupt Enable Register
Interrupt Status/Clear Register
S/PDIF Receive Data - left channel
S/PDIF Receive Data - right channel
S/PDIF Receive C channel, bits [47:24]
S/PDIF Receive U channel
S/PDIF Receive Q channel
S/PDIF Transmit Left channel
S/PDIF Transmit Right channel
S/PDIF Transmit Cons. C channel,
bits [47:24]
S/PDIF Transmit Cons. C channel,
bits [23:0]
S/PDIF Transmit Prof. C channel,
bits [31:24]
S/PDIF Transmit Prof. C channel, bits [23:0]
FreqMeasurement
Transmit Clock Control Register
Description
Size Valid Reset
Bits Bits Value
24 [23:0] 0x000400
24 [1] 0x000000
24 [5:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000002
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [7:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x000000
24 [23:0] 0x020f00
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