Freescale Semiconductor Symphony DSP56724 Reference Manual page 345

Bits Name
23–16 — Reserved
15 BA Base address bit 13. The upper 11 bits of each base address register are compared to the address
on the address bus to determine if the bus master is accessing a memory bank controlled by the
memory controller. This is used with the address mask bits ORx[AM].
14–13 XBA Extended base address. BA are compared with the address bus only for a given type of access: X
access, Y access, P access (read/write) or P access (instruction fetch). This is used with the
extended address mask bits ORx[XAM].
00 Response X access
01 Response Y access
10 Response P access (read/write)
11 Response P access (instruction fetch)
12–9 — Reserved
8 WP Write protect
0
1
7–5 MSEL Machine select. Specifies which machine to use for the memory operations handling. Reset value
selects GPCM.
000 GPCM
001 Reserved
010 Reserved
011 SDRAM
100 UPMA
101 UPMB
110 UPMC
111 Reserved
4-1 — Reserved
0 V Valid bit. Indicates that the contents of the BRx and ORx pair are valid. The LCSx signal does not
assert unless V is set (an access to a region that has no valid bit set may cause a bus time-out). After
a system reset, only BR0[V] is set.
0 This bank is invalid.
1 This bank is valid.
21.3.2.2 Option Registers (OR0–OR7)
The ORx registers define the sizes of the memory banks and access attributes. The ORx attribute bits
support the following three modes of operation as defined by BRx[MSEL]:
• GPCM mode
• UPM mode
• SDRAM mode
The ORx registers are interpreted differently depending on which of the three machine types is selected
for that bank.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 21-7. BRL x Field Descriptions
Read and write accesses are allowed.
Only read accesses are allowed. The memory controller does not assert LCSx on write cycles to
this memory bank. TESR[WP] is set (if enabled) if a write to this memory bank is attempted, and
a external memory error interrupt is generated (if enabled), terminating the cycle.
External Memory Controller (EMC)
Description
21-11