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Clock Generation Module (CGM)
Shared Peripheral Bus
Extal
Core-0 Stop or Wait mode
Core-1 Stop or Wait mode
Related clocks can be
stopped when Core-0 or
Core-1 get into a STOP or
WAIT mode.
7.1.2
Features
The CGM includes the following features:
•
Allows changing the low-power divide factor (DF = 2
•
Provides glitch-free output clocks to DSP Cores and peripherals.
•
Provides a wide range of system clocks.
•
Performs power-saving by gating clocks for both cores and peripherals.
7.1.3
Modes of Operation
The CGM provides all necessary clocks to the DSP56724/DSP56725 devices. For stable operations, the
system clock is defined in
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
7-2
CGM
PLL Control Registers
Internal PLL
-Clock input division
-Frequency multiplication
-Skew elimination
Low Power Divider
i
(2
, i=0–7
Core-0
Core-1
Gating Cells
Gating Cells
Clocks to
Clocks to
Core-0
Core-1
Figure 7-1. CGM Function Diagram
Table
7-1.
PLL Out (FOUT raw)
internal_clk
Shared
Gating Cells
Clocks to blocks shared by
Core-0 and Core-1
i
, i = 0–7) without losing lock.
The PLL is configurable over
the Shared Peripheral bus,
which both Core-0 and
Core-1 can access.
The PLL output clock can be
further divided by the Low
Power Divider for power
saving.
Freescale Semiconductor
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