Freescale Semiconductor Symphony DSP56724 Reference Manual page 349

Bits Name
3 SETA External address termination.
0 Access is terminated internally by the memory controller unless the external device asserts LGTA earlier
to terminate the access.
1 Access is terminated externally by asserting the LGTA external pin. (Only LGTA can terminate the
access).
2 TRLX Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals.
0 Normal timing is generated by the GPCM.
1 Relaxed timing on the following parameters:
• Adds an additional cycle between the address and control signals (only if ACS is not equal to 00).
• Doubles the number of wait states specified by SCY, providing up to 30 wait states.
• Works in conjunction with EHTR to extend hold time on read accesses.
• LCSx (only if ACS is not equal to 00) and LWE signals are negated one cycle earlier during writes.
1 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
0 EAD External address latch delay. Allows extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
CRR[EADC]).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 21-12. ORL x -GPCM Field Descriptions (Continued)
TRLX EHTR
0 0 The memory controller generates normal timing. No
additional cycles are inserted.
0 1 1 idle clock cycle is inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
External Memory Controller (EMC)
Description
Meaning
21-15