Freescale Semiconductor Symphony DSP56724 Reference Manual page 381

Table 21-68. GPCM Read Control Signal Timing for CRR[CLKDIV] = 2
Option Register Attributes
TRLX
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Total cycles when LALE is asserted for one cycle only (ORx[EAD]=0; ORx[EAD]=1 and
CRR[EADC]=01). Asserting LALE for more than one cycle increases the total cycle
count accordingly.
21.4.2.2 Chip-Select Assertion Timing
The banks (selected to work with the GPCM) support an option to drive the LCSx signal with different
timings (with respect to the external address and data bus). LCSx can be driven in any of the following
ways:
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
EHTR XACS ACS
LCSx Asserted
0 0 00
0 0 10
0 0 11
0 1 00
0 1 10
0 1 11
1 0 00
1 0 10
1 0 11
1 1 00
1 1 10
1 1 11
0 0 00
0 0 10
0 0 11
0 1 00
0 1 10
0 1 11
1 0 00
1 0 10
1 0 11
1 1 00
1 1 10
1 1 11
Signal Behavior (Bus Clock Cycles)
Address to LCSx Negated to
Address Change
0 1
1/2 1
1/2 1
0 1
1 1
2 1
0 2
1/2 2
1/2 2
0 2
1 2
2 2
0 5
1+1/2 5
1+1/2 5
0 5
2 5
3 5
0 9
1+1/2 9
1+1/2 9
0 9
2 9
3 9
External Memory Controller (EMC)
1
Total Cycles
4+SCY
4+SCY
4+SCY
4+SCY
4+SCY
5+SCY
5+SCY
5+SCY
5+SCY
5+SCY
5+SCY
6+SCY
8+2*SCY
9+2*SCY
9+2*SCY
8+2*SCY
9+2*SCY
10+2*SCY
12+2*SCY
13+2*SCY
13+2*SCY
12+2*SCY
13+2*SCY
14+2*SCY
21-47