Cdtext Control Register (Srcd) - Freescale Semiconductor Symphony DSP56724 Reference Manual

S/PDIF—Sony/Philips Digital Interface
Table 18-3. S/PDIF Configuration Register (SCR) Fields (Continued)
Bit
7, 6 RcvSrc_Sel
5 ValCtrl
4, 3, 2 TxSel
1, 0 USrc_Sel
18.2.2

CDText Control Register (SRCD)

Address X:$FFFF61
23 22
R
W
Reset 0 0
11 10
R
W
Reset 0 0
Table 18-4. CDText Control Register (SRCD) Field Descriptions
Bit
23–2 Reserved
1 USyncMode
0 Reserved
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
18-6
Field
Rcv Source Select
00 S/PDIF in 1
01 Reserved
10 Reserved
11 Reserved
0 Outgoing Validity always set
1 Outgoing Validity always clear
000 Off and output 0
001 Feed-through SPDIFIN1
010 Reserved
011 Reserved
100 Reserved
101 Normal operation
U Channel Source Select
00 No embedded U channel
01 U channel from S/PDIF receive block (CD mode)
10 Reserved
11 U channel from on chip transmitter
21 20 19
9'b0
0 0 0
9 8 7
0 0 0
Figure 18-4. CDText Control Register (SRCD)
Field
Bits 23–15 and 7–3 return zeros when read.
0 Non-CD data
1 CD user channel subcode
Description
18 17 16
0 0 0
6 5 4
5'b0
0 0 0
Description
Access: User Read/Write
15 14 13
0 0 0
3 2 1
USyncMode
0 0 0
Freescale Semiconductor
12
0
0
0