Freescale Semiconductor Symphony DSP56724 Reference Manual page 268

S/PDIF—Sony/Philips Digital Interface
• Channel status transmission registers: SPDIFTxCChannelCons_h (STCSCH),
SPDIFTxCChannelCons_l (STCSCL), SPDIFTxCChannelProf_h (STCSPH),
SPDIFTxCChannelProf_l (STCSPL)
Address X:$FFFF6B
23 22 21 20
R
W
Reset 0 0 0
Bit Field
23–0 TxDataLeft
Address X:$FFFF6C
23 22 21 20
R
W
Reset 0 0 0
Bit Field
23–0 TxDataRight
Address X:$FFFF6D
23 22 21 20
R
W
Reset 0 0 0
Table 18-15. SPDIFTxCChannelCons_h Register (STCSCH) Fields
Bit Field
23–0 TxCChannelCons_h
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
18-12
19 18 17 16 15 14 13
0 0 0 0 0 0
Figure 18-15. SPDIFTxLeft Register (STL)
Table 18-13. SPDIFTxLeft Register (STL) Fields
S/PDIF transmit left channel data
It is write-only, and always returns zeros when read.
19 18 17 16 15
0 0 0 0 0 0
Figure 18-16. SPDIFTxRight Register (STR)
Table 18-14. SPDIFTxRight Register (STR) Fields
S/PDIF transmit right channel data
It is write-only, and always returns zeros when read.
19 18 17 16 15
0 0 0 0 0 0
Figure 18-17. SPDIFTxCChannelCons_h Register (STCSCH)
S/PDIF Transmit Cons. C channel data
Contains first 24 bits without interpretation.
When read, it returns the latest data written by the processor.
12 11 10 9
24'b0
TxDataLeft
0 0 0 0 0 0
Description
14 13 12 11 10 9
24'b0
TxDataRight
0 0 0 0 0 0
Description
14 13 12 11 10 9
TxCChannelCons_h
0 0 0 0 0 0
Description
Access: User Write
8 7 6 5 4 3
0 0 0 0 0 0
Access: User Write
8 7 6 5 4 3
0 0 0 0 0 0
Access: User Read/Write
8 7 6 5 4 3
0 0 0 0 0 0
Freescale Semiconductor
2 1 0
0 0 0
2 1 0
0 0 0
2 1 0
0 0 0