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Shared Bus Arbiter
14.2
Memory Map and Register Definition
There are no registers or memory in this block.
14.3
Functional Description
The following sections describe the arbiter functionality.
14.3.1
Shared Bus Arbitration
The arbitration process involves the masters and the arbiter. The masters arbitrate on the privilege to own
the address tenure. For the data tenure, the arbiter uses the same order of transactions as address tenures.
14.3.1.1
Configuring the Arbitration Method
When Shared Bus access contention occurs, the Arbiter Control Register (ARCR) in the chip configuration
module determines the arbitration method. Three static arbitration methods are supported: Shared Bus
Master 0 always has priority, Shared Bus Master 1 always has priority, and the round-robin method (the
bus masters take turns getting bus access). See the
about the ARCR register.
14.3.1.2
Shared Bus Master 0/1 Always Has Priority Methods
When either Shared Bus Master 0 or Shared Bus Master 1 has priority, a Shared Bus access request from
the master with priority is always granted first. The access sequences for this type of static arbitration
based on priority for Master 0 or Master 1 are shown in
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
14-2
Chapter 20, "Chip Configuration Module,"
Figure 14-2
and
Figure
for more
14-3.
Freescale Semiconductor
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