Freescale Semiconductor Symphony DSP56724 Reference Manual page 243

System Clock
Master-0 Req
Master-0 Access
Master-1 Req
Master-1 Access
Arbiter Out
Note: All accesses are assumed to
finish with 0 wait states after the
arbitration has occurred.
14.3.1.4 Cores/DMA Continuous Access Arbitration
The arbiter has specific arbitration behavior for continuous access from a DSP core or DMA.
A core access introduced by a core RMW (read-modify-write) instruction means that the next access must
be by the same core, and will cause the Shared Bus Arbiter to reserve the next access for the same Shared
Bus master. This behavior implies that one core RMW operation cannot be interrupted by the other Shared
Bus masters (the other DSP core or DMA).
DMA continuous access can be set by configuring the corresponding DMA channel control register. If a
DMA continuous access has priority over the other Shared Bus master, then the Shared Bus master must
wait until one cycle after the DMA continuous access has completed, before it takes the access.
For shared memory access, DMA continuous access is ignored (the core RMW instruction is not ignored).
If DMA uses continuous access to the shared memory, the DMA continuous access is regarded as normal
access by the shared memory.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
M0-1 M0-2
M1-1 M1-2
Master-1 Master-1
M0-1 M1-1 M0-2
Master-0 Master-0
Figure 14-4. Round-Robin Arbitration Method
M0-3 M0-4
M1-2 M0-3
Master-0 Master-0
Shared Bus Arbiter
M0-5
M1-3 M1-4
Master-1 Master-1
M0-4 M1-3 M0-5 M1-4
Master-0
14-5