Freescale Semiconductor Symphony DSP56724 Reference Manual page 197

Connecting the HREQ line between two SHI-equipped DSPs enables full hardware handshaking (if
CPHA = 1), with one DSP operating as an SPI master device and the other DSP operating as an SPI slave
device. For CPHA = 0, HREQ should be disabled by clearing the HRQE[1:0] bits.
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10.6.3 I C Slave Mode
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Initiate I C slave mode by performing the following steps:
1. Set HEN = 1 to enable the SHI.
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2. Set HI C = 1 to select the I
3. Set HMST = 0 to select the slave mode of operation.
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In I C slave mode, the contents of the HCKR register are ignored, and the SHI external pins operate as
follows:
• SCK/SCL is the SCL serial clock input.
• MISO/SDA is the SDA open drain serial data line.
• MOSI/HA0 is the HA0 slave device address input.
• SS/HA2 is the HA2 slave device address input.
• HREQ is the Host Request output.
When the SHI is enabled and configured in I
lines to detect a start event. After detecting a start event, the SHI receives the slave device address byte
and enables the slave device address recognition unit:
• If the slave device address byte was not identified as its personal address, then the SHI controller
fails to acknowledge this byte by not driving the SDA line low at the 9th clock pulse (ACK = 1).
However, the SHI controller continues to poll the SDA and SCL lines to detect a new start event.
• If the slave device address byte was identified as its personal address (if the personal slave device
address was correctly identified), then the slave device address byte is acknowledged (ACK = 0 is
sent), and a receive/transmit session is initiated according to the 8th bit (R/W) of the received slave
device address byte.
10.6.3.1 Receive Data in I
A receive session is initiated when the personal slave device address has been correctly identified and the
R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in
the SDA line is shifted (MSB first) into the IOSR register. Following each received byte, an acknowledge
(ACK = 0) is sent at the 9th clock pulse via the SDA line. Data is acknowledged byte-wise, as required by
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the I C bus protocol, and is transferred to the HRX FIFO when the complete word (according to the
HM[1:0] bits) is loaded into the IOSR register. It is the programmer's responsibility to select the correct
number of bytes in an I
slave device address byte does not count as part of the data; the slave device address byte is treated
separately.
In a receive session, only the receive path is enabled and HTX-register-to-IOSR-register transfers are
inhibited. The HRX FIFO contains valid data, which may be read by the DSP using either DSP instructions
or DMA transfers (if the HRNE status bit is set).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
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C mode.
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C slave mode, the SHI controller inspects the SDA and SCL
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C Slave Mode
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C frame so that they fit into a complete number of words. For this purpose, the
Serial Host Interface (SHI, SHI_1)
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