Register Descriptions - Freescale Semiconductor Symphony DSP56724 Reference Manual

18.2

Register Descriptions

18.2.1 S/PDIF Configuration Register (SCR)
Address X:$FFFF60
23 22
R
RcvFifo RcvFifo
_Ctrl _Off/On
W
Reset 0 0
11 10
R
TxFifo_Ctrl
W
Reset 0 1
Bit
23 RcvFifo_Ctrl
22 RcvFifo_Off/On
21 RcvFifo_Rst
20, 19 RcvFifoFull_Sel
18 RcvAutoSync
17 TxAutoSync
16–12 Reserved
11, 10 TxFifo_Ctrl
9 PDIR_Rcv
8 PDIR_TX
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
21 20 19
RcvFifo_
RcvFifoFull_Sel
Rst
0 0 0
9 8 7
RcvSrc_Sel
PDIR_Rcv PDIR_Tx
0 0 0
Figure 18-3. S/PDIF Configuration Register (SCR)
Table 18-3. S/PDIF Configuration Register (SCR) Fields
Field
0 Normal operation
1 Always read zero from rcv data register
0 S/PDIF Rcv FIFO is on
1 S/PDIF Rcv FIFO is off. Does not accept data from interface
0 Normal operation
1 Reset register to 1 sample remaining
00 Full interrupt if at least 1 sample in FIFO
01 Full interrupt if at least 2 sample in FIFO
10 Full interrupt if at least 3 sample in FIFO
11 Full interrupt if at least 6 sample in FIFO
0 Rcv FIFO auto sync off
1 Rcv FIFO auto sync on
0 Tx FIFO auto sync off
1 Tx FIFO auto sync on
00 Send out digital zero on S/PDIF Tx
01 Normal operation
10 Reset to 1 sample remaining
11 Reserved
DMA Receive Request (PDIR1 FIFO full)
DMA Transmit Request (Transmit FIFO empty)
S/PDIF—Sony/Philips Digital Interface
18 17 16
RcvAuto TxAuto
Sync Sync
0 0 0
6 5 4
ValCtrl
0 0 0
Description
Access: User Read/Write
15 14 13
0 0 0
3 2 1
TxSel USrc_Sel
0 0 0
12
0
0
0
18-5