Freescale Semiconductor Symphony DSP56724 Reference Manual page 232

Inter-Core Communication (ICC)
13.2.2.8 ICDR4 (ICC Data Register 4)
The ICDR4 Data Register is shown in
Address Y:FFFFD4
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–0 Communication Data
13.2.2.9 ICCR4 (ICC Control Register 4)
The ICCR4 Control Register is shown in
Address Y:FFFFD3
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–4 Reserved Write 0 to ensure future compatibility.
3 EIE Error Interrupt Enable bit that reflects the status of the same bit of the other core's ICCR3 register.
2 EF Error Interrupt Flag that reflects the status of the same bit of the other core's ICCR3 register.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
13-10
Figure
21 20
0 0 0
9 8
0 0 0
Figure 13-10. ICDR4 Data Register
Table 13-10. ICDR4 Field Descriptions
Read-only communication data that reflects the other core's ICDR3 data register.
Figure
21 20
0 0 0
9 8
0 0 0
Figure 13-11. ICCR4 Control Register
Table 13-11. ICCR4 Field Descriptions
13-10.
19 18 17
Communication Data
0 0 0
7 6 5
Communication Data
0 0 0
Description
13-11.
19 18 17
0 0 0
7 6 5
0 0 0
Description
Access: User Read
16 15 14
0 0 0
4 3 2
0 0 0
Access: User Read
16 15 14
0 0 0
4 3 2
EIE EF
0 0 0
Freescale Semiconductor
13 12
0 0
1 0
0 0
13 12
0 0
1 0
MIF MIE
0 0