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23
Name
11
ARCR
R
Y:FFFFE0
W
R
W
20.2.2
Register Descriptions
20.2.2.1
Reserved Register
This register is a 24-bit Read-only register. See
Address Y:FFFFE7
23
22
R
W
Reset
0
11
10
R
W
Reset
0
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 20-2. CFG Register Summary (Continued)
22
21
20
10
9
8
21
20
0
0
0
9
8
0
0
0
Figure 20-1. Reserved Control Register
Table 20-3. Field Description
Bit
Field
23–0
Reserved
19
18
17
16
7
6
5
4
Shared Bus Arbiter Control
Shared Bus Arbiter Control
Figure
20-1.
19
18
17
0
0
0
7
6
5
0
0
0
Description
Chip Configuration Module
15
14
3
2
Access: User Read
16
15
14
0
0
0
4
3
2
0
0
0
13
12
1
0
13
12
0
0
1
0
0
0
20-3
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