Freescale Semiconductor Symphony DSP56724 Reference Manual page 377

EMC
in GPCM Mode
Figure 21-5 shows LCS as defined by the setup time required between the address lines and CE. You can
configure ORx[ACS] to specify LCS to meet this requirement.
LCLK
LAD
LALE
A[23:0]
LCSx
LOE
21.4.2.1 Timing Configuration
If BRx[MSEL] selects the GPCM, the attributes for the memory cycle are taken from ORx. These
attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR and SETA fields.
behavior and system response for a write access with CRR[CLKDIV] = 4 or CRR[CLKDIV] = 8.
Table 21-66 shows the signal behavior and system response for a read access with CRR[CLKDIV] = 4 or
CRR[CLKDIV] = 8 for both personalities.
behavior respectively, when CRR[CLKDIV] = 2.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
LCSx
LOE
LWE
LA[2:0]
LALE
LAD[23:0]
Figure 21-4. Local Bus to GPCM Device Interface
Address
ACS = 10 ACS = 11
TA
Figure 21-5. GPCM Basic Read Timing
(XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)
Table 21-67
CE
OE
WE
A[2:0]
A[23:3]
Latch
Data[7:0]
Read Data
Latched Address
and Table 21-68
External Memory Controller (EMC)
Memory/Peripheral
24-bit port
SRAM
Table 21-65 shows signal
show the write and read signal
21-43