Freescale Semiconductor Symphony DSP56724 Reference Manual page 418

External Memory Controller (EMC)
LCLK
LAD
Address
LALE
A
TA
Row LSBs
LA
RAS
CAS
R/W
LBCTL
Figure 21-46. Burst Read Access to FPM DRAM Using LOOP (2 Beats Shown)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-84
Address
Row
cst1 Bit 0 0
cst2 Bit 1 0
cst3 Bit 2 0
cst4 Bit 3 0
Reserved Bit 4 1
Reserved Bit 5 1
Reserved Bit 6 1
Reserved Bit 7 1
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t1 Bit 12 1
g1t3 Bit 13 1
g2t1 Bit 14
g2t3 Bit 15
g3t1 Bit 16
g3t3 Bit 17
g4t1 Bit 18
g4t3 Bit 19
g5t1 Bit 20
g5t3 Bit 21
redo[0] Bit 22
redo[1] Bit 23
loop Bit 24 0
exen Bit 25 0
amx0 Bit 26 1
amx1 Bit 27 0
na Bit 28 0
uta Bit 29 0
todt Bit 30 0
last Bit 31 0
RBS RBS
Data 1
Column 1
Column 1 LSBs
0
0
LALE 0
0
pause
1
(due to
1
change in
1
AMX)
0
1
1
1
0
0
0
0
0
0
0
RBS+
RBS+1
Data 2
Column 2
Column 2 LSBs
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 1
1 1
1 0
1 0
0 0
0 0
1 0
1 0
0 1
0 1
RBS+
2 3
Freescale Semiconductor