Freescale Semiconductor Symphony DSP56724 Reference Manual page 393

21.4.3.6 SDRAM Address Multiplexing
The lower bits of the address bus are connected to the memory device's address port, with the memory
controller multiplexing the row/column and the internal bank select lines. The position of the bank select
lines are set according to SDMR[BSMA].
address down to the lower output address signals during activate and shifts the bank select bits up to the
address pins specified by SDMR[BSMA].
Logical Address:
Activate Address (RAS):
R/W Address (CAS):
Note that during normal operation (read/write), a full 24-bit address which includes row and column, is
generated on the LAD[23:0] signals. However, address and data signal multiplexing implies that the
address must be latched by an external latch that is controlled by LALE. All SDRAM device address
signals must be connected to the latched address bits and burst address bits (LA[2:0]) of the EMC, with
the exception of A10, which has a dedicated connection on LSDA10. LSDA10 is driven with the
appropriate row address bit for SDRAM commands that require A10 to be an address.
21.4.3.7 SDRAM Device-Specific Parameters
The software is responsible for setting correct values for device-specific parameters that can be extracted
from the device's data sheet. The values are stored in the ORx and SDMR registers. These parameters
include the following:
• Precharge-to-activate interval (SDMR[PRETOACT])
• Activate-to-read/write interval (SDMR[ACTTORW])
• CAS latency, column address to first-data-out (SDMR[CL] and CRR[ECL])
• Write recovery, last-data-in to precharge (SDMR[WRC])
• Refresh recovery interval (SDMR[RFRC])
• External buffers on the control lines present (SDMR[BUFCMD] and CRR[BUFCMDC])
In addition, the EMC hardware ensures a default activate to precharge interval of 10 bus cycles. The
following sections describe SDRAM parameters programmed in SDMR.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Figure 21-16
23
MSBs
ROW
ROW
Figure 21-16. SDRAM Address Multiplexing
External Memory Controller (EMC)
shows how the SDRAM controller shifts the row
BS COLUMN
BS ROW
—
COLUMN
BS
To memory device pins, except A10
0
21-59