Freescale Semiconductor Symphony DSP56724 Reference Manual page 155

9.2.5.3 SAICR Serial Output Flag 2 (OF2)—Bit 2
The Serial Output Flag 2 (OF2) is a data bit used to hold data to be send to the OF2 pin. When the ESAI
is in the synchronous clock mode (SYN=1), the HCKR pin is configured as the ESAI flag 2. If the receiver
high frequency clock direction bit (RHCKD) is set, the HCKR pin is the output flag OF2, and data present
in the OF2 bit is written to the OF2 pin at the beginning of the frame in normal mode or at the beginning
of the next time slot in network mode.
9.2.5.4 SAICR Reserved Bits—Bits 5–3, 23–9
These bits are reserved. They read as zero, and they should be written with zero for future compatibility.
9.2.5.5 SAICR Synchronous Mode Selection (SYN)—Bit 6
The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the
ESAI operate synchronously or asynchronously with respect to each other (see
cleared, the asynchronous mode is chosen and independent clock and frame sync signals are used for the
transmit and receive sections. When SYN is set, the synchronous mode is chosen and the transmit and
receive sections use common clock and frame sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section
clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins
SCKR, FSR and HCKR now operate as I/O flags. See
of SYN on the receiver clock pins.
9.2.5.6 SAICR Transmit External Buffer Enable (TEBE)—Bit 7
The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when in the
synchronous mode. If the ESAI is configured for operation in the synchronous mode (SYN=1), and TEBE
is set while FSR pin is configured as an output (RFSD=1), the FSR pin functions as the transmitter external
buffer enable control to enable the use of an external buffers on the transmitter outputs. If TEBE is cleared,
the FSR pin functions as the serial I/O flag 1. See
FSR pin.
9.2.5.7 SAICR Alignment Control (ALC)—Bit 8
The ESAI is designed for 24-bit fractional data, thus shorter data words are left aligned to the MSB (bit
23). Some applications use 16-bit fractional data. In those cases, shorter data words may be left aligned to
bit 15. The Alignment Control (ALC) bit supports these applications.
If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and receive shift
registers. If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and
receive shift registers.
While ALC is set, 20-bit and 24-bit words may not be used, and word length
control should specify 8-, 12-, or 16-bit words; otherwise, results are
unpredictable.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
Table 9-7, Table 9-8
Table 9-8 for a summary of the effects of TEBE on the
NOTE
Table 9-11). When SYN is
and Table 9-9 for the effects
,
9-33