Freescale Semiconductor Symphony DSP56724 Reference Manual page 233

Bit Field
1 MIF Maskable Interrupt Flag that reflects the status of the same bit of the other core's ICCR3 register.
1: Interrupt Flag is set
0: Interrupt Flag is cleared
0 MIE Interrupt Enable bit that reflects the status of the same bit of the other core's ICCR3 register.
1: Interrupt is Enabled
0: Interrupt is Disabled
13.2.2.10 ICAR4 (ICC Acknowledge Register 4)
The ICAR4 Register is shown in
Address Y:FFFFD2
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–2 Reserved
1 RACK
0 ACK
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 13-11. ICCR4 Field Descriptions (Continued)
Figure 13-12.
21 20
0 0 0
9 8
0 0 0
Figure 13-12. ICAR4 Control Register
Table 13-12. ICAR4 Field Descriptions
Write 0 to ensure future compatibility.
Reflects the value of the RACK bit in the other core's ICAR3 register.
Reflects the value of the ACK bit in the other core's ICAR3 register.
Description
19 18 17
0 0 0
7 6 5
0 0 0
Description
Inter-Core Communication (ICC)
Access: User Read
16 15 14
0 0 0
4 3 2
RACK
0 0 0
13 12
0 0
1 0
ACK
0 0
13-11