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Serial Host Interface (SHI, SHI_1)
2
10.5.2
I
C Data Transfer Formats
2
I
C bus data transfers follow the following process: after the start event, a slave device address is sent. The
address consists of 7 address bits and an 8th bit as a data direction bit (R/W). In the data direction bit, "0"
indicates a transmission (write), and "1" indicates a request for data (read). A data transfer is always
terminated by a stop event generated by the master device. However, if the master device still wishes to
communicate on the bus, it can generate another start event and address another slave device without first
generating a stop event. (The SHI does not support this feature when operating as an I
This method is also used to provide indivisible data transfers. Various combinations of read/write formats
are illustrated in
Figure 10-10
S
Slave Address
Start
Bit
S
Slave Address
Start
Bit
The first data byte in a write-bus cycle can be used as a user-predefined
control byte (for example, to determine the location where the forthcoming
data bytes should be transferred to).
10.6
SHI Programming Considerations
The SHI implements both SPI and I
or a single-master device. After the operating mode is selected, the SHI may communicate with an external
device by receiving and/or transmitting data. Before changing the SHI operating mode, an SHI individual
reset should be generated by clearing the HEN bit. The following sections describe programming
considerations for each operating mode.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
10-20
and
Figure
10-11.
ACK from
Slave Device
0
A
First Data Byte
R/W
2
Figure 10-10. I
C Bus Protocol For Host Write Cycle
ACK from
Slave Device
1
A
Data Byte
R/W
N = 0 to M
Data Bytes
2
Figure 10-11. I
C Bus Protocol For Host Read Cycle
NOTE
2
C bus protocols, and can be programmed to operate as a slave device
ACK from
Slave Device
A
Data Byte
N = 0 to M
Data Bytes
ACK from
Slave Device
A
Last Data Byte
2
C master device.)
ACK from
Slave Device
A
S, P
Start or
Stop Bit
AA0425
No ACK from
Master Device
1
P
Stop
Bit
AA0426
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