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External Memory Controller (EMC)
21.1.1
Features
Major features of the External Memory Controller (EMC) include:
•
Generic features
— Eight memory chip select pins (supports eight memory banks)
— Accessible from the entire X, Y and P address space
— Variable memory block sizes (8 K words to 16 M words)
— Address and data share the LAD[23:0]
— Selection of the memory controller among SDRAM, GPCM and UPM is on per-bank basis
— Data buffer controls are activated on a per-bank basis
— Write protection error detection
— Chip select error detection
— Bus timeout error detection
•
Synchronous DRAM (SDRAM) machine
— Provides the control functions and signals to any JEDEC-compliant SDRAM device
— Up to 100 SDRAM clock
— Four caches for active pages
— Supports 4-way bank interleaving
— Supports 24-bit SDRAM port size
•
General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, FEPROM, and other peripherals
— Supports boot from external memory connected at LCS0 (at system reset)
— Supports boot from 8-bit or 24-bit devices
— External access termination signal (GTA)
•
Three User-Programmable Machines (UPMs)
— User-specified control-signal patterns can be initiated by software
— User-specified control-signal patterns can be run when an internal master requests a single-beat
or burst read or write access.
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— Each UPM can be defined to support DRAM devices with depths of 64 Kw, 128 Kw, 256 Kw,
512 Kw, 1 Mw, 2 Mw, 4 Mw, 8 Mw and 16 Mw.
— Supports 24-bit memory port size
— External UPM handshake input—asynchronous freeze/restart, or synchronous transfer
acknowledge
•
De-skew Phase-locked Loop (PLL)
— Uses de-skew PLL to automatically compensate for PCB wire delay
— User-programmable PLL bypass enable
— User-programmable PLL power down
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-2
Freescale Semiconductor
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