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Serial Host Interface (SHI, SHI_1)
Clock control logic allows a selection of clock polarity and a choice of two fundamentally different
clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI
is configured as a master, the control bits in the HCKR register select the appropriate clock rate, as well
as the desired clock polarity and phase format. (See
The SS line allows selection of an individual slave SPI device; slave devices that are not selected do not
interfere with SPI bus activity—they keep their MISO output pin in the high-impedance state. When the
SHI is configured as an SPI master device, the SS line should be held high. If the SS line is driven low
when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set).
10.5
Characteristics Of The I
2
The I
C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for clock signals
(SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
2
In the I
fast mode (400 kHz clock rate) are defined. The SHI can operate in either
standard or fast mode.
10.5.1
Overview
2
The I
C bus protocol must conform to the following rules:
•
Data transfers may be initiated only when the bus is not busy.
•
During data transfers, the data line must remain stable whenever the clock line is high. Changes in
the data line when the clock line is high are interpreted as control signals (see
SDA
SCL
2
The I
C bus protocol defines the following events:
•
Bus not busy—Both data and clock lines remain high.
•
Start data transfer—The start event is defined as a change in the state of the data line, from high to
low, while the clock is high (see
•
Stop data transfer—The stop event is defined as a change in the state of the data line, from low to
high, while the clock is high (see
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
10-18
2
C bus specifications, the standard mode (100 kHz clock rate) and a
Data Line is Stable:
Data is Valid
Figure 10-7. I
Figure
Figure
Figure
10-6.)
C Bus
NOTE
Change of
Data Allowed
2
C Bit Transfer
10-8).
10-8).
Figure
10-7).
AA0422
Freescale Semiconductor
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