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Triple Timer Module (TEC, TEC_1)
GDB
24
Timer Prescaler
Load Register
CLK/2
11.2
Individual Timer Block Diagram
Figure 11-2
shows the structure of an individual timer block. The DSP56724/DSP56725 treats each timer
as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory
space. The three timers are identical in structure and function. Either standard polled or interrupt
programming techniques can be used to service the timers. A single, generic timer is discussed in this
chapter. Each timer includes the following:
•
24-bit counter
•
24-bit read/write Timer Control and Status Register (TCSR)
•
24-bit read-only Timer Count Register (TCR)
•
24-bit write-only Timer Load Register (TLR)
•
24-bit read/write Timer Compare Register (TCPR)
•
Logic for clock selection and interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a description of timer mode
operations, see
Section 11.4, "Operating
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
11-2
24
TPLR
TPCR
Timer Prescaler
Count Register
24-bit Counter
Figure 11-1. Triple Timer Block Diagram
Mode."
24
Timer 0
Timer 1
Timer 2
24
Freescale Semiconductor
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