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Core Configuration
5.4
DSP Cores Operating Modes
The operating modes are defined in
MD bits are latched from the MODA0, MODB0, MODC0, and MODD0 pins. During reset, Core-1's
OMR:MA, MB, MC, MD bits are latched from MODA1, MODB1,MODC1, and MODD1 pins.
DSP56724 External Pins
MODD0
MODC0
OMR:MD
OMR:MC
Mode
0
0
0
1
0
0
2
0
0
3
0
0
4
0
1
5
0
1
6
0
1
7
0
1
8
1
0
9
1
0
A
1
0
B
1
0
C
1
1
D
1
1
E
1
1
F
1
1
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
5-6
Table 5-5
and
Table 5-6.
Table 5-5. Core-0 Operating Modes in DSP56724
MODB0
MODA0
Reset
OMR:MB
OMR:MA
Vector
0
0
$FF_FFFE Boot via SHI (SPI)
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
During reset, Core-0's OMR: MA, MB, MC,
Description
Boot via SHI (I2C Filter)
Jump to PROM (SPI)
Jump to PROM (I2C Filter)
Boot via Core-1
Boot via SHI Master (SPI-EEPROM)
Boot via SHI Master (I2C-EEPROM)
Boot via GPIO Master (SPI-EEPROM)
PE6/PE7/PE8/PE9
Boot via External Memory word-wide.
Not available for DSP56725.
Boot via External Memory byte-wide.
Not available for DSP56725.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Freescale Semiconductor
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