Freescale Semiconductor Symphony DSP56724 Reference Manual page 64

Memory Map
Peripherals
EMC
1
Includes short name and long name.
Peripherals Address
GPIO PORT G Y:$FF_FFFF
Y: $FF_FFFE
Y: $FF_FFFD
Y: $FF_FFFC
Y:$FF_FFFB
Y: $FF_FFFA
Y: $FF_FFF9
Y: $FF_FFF8
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
3-12
Table 3-7. Detailed Device X-Memory Map (Continued)
Address
X: $FF_FE0F EMC Options Register 3 high part (ORH3)
X: $FF_FE0E EMC Options Register 3 low part (ORL3)
X: $FF_FE0D EMC Base Register 3 high part (BRH3)
X: $FF_FE0C EMC Base Register 3 low part (BRL3)
X: $FF_FE0B EMC Options Register 2 high part (ORH2)
X: $FF_FE0A EMC Options Register 2 low part (ORL2)
X: $FF_FE09 EMC Base Register 2 high part (BRH2)
X: $FF_FE08 EMC Base Register 2 low part (BRL2)
X: $FF_FE07 EMC Options Register 1 high part (ORH1)
X: $FF_FE06 EMC Options Register 1 low part (ORL1)
X: $FF_FE05 EMC Base Register 1 high part (BRH1)
X: $FF_FE04 EMC Base Register 1 low part (BRL1)
X: $FF_FE03 EMC Options Register 0 high part (ORH0)
X: $FF_FE02 EMC Options Register 0 low part (ORL0)
X: $FF_FE01 EMC Base Register 0 high part (BRH0)
X: $FF_FE00 EMC Base Register 0 low part (BRL0)
X: $FF_FDFF Reserved
to
X: $FF_F000
Table 3-8. Detailed Device Y-Memory Map
Reserved
Port G Control Register 1(PCRG1)
Port G GPIO Direction Register 1(PRRG1)
Port G GPIO Data Register 1(PDRG1)
Reserved
Port G Control Register (PCRG)
Port G GPIO Direction Register (PRRG)
Port G GPIO Data Register (PDRG)
1
Register Name
1
Register Name
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