Freescale Semiconductor Symphony DSP56724 Reference Manual page 134

Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
RDC0–RDC4
RX WORD
CLOCK
RECEIVER
FRAME RATE
DIVIDER
RECEIVE
CONTROL
LOGIC
TDC0–TDC4
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
TRANSMIT
CONTROL
LOGIC
Figure 9-4. ESAI Frame Sync Generator Functional Block Diagram
9.2.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0)—Bits 17–14
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the transmitter
serial bit clock when the source of the high frequency clock and the bit clock is the internal DSP clock.
When the HCKT input is being driven from an external high frequency clock, the TFP3–TFP0 bits specify
an additional division ratio in the clock divider chain.
Figure 9-3 shows the ESAI high frequency clock generator functional diagram.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
9-12
RFSL
INTERNAL RX FRAME CLOCK
SYNC
TYPE
SYN=0
RECEIVE
FRAME SYNC
SYN=1
TFSL
INTERNAL TX FRAME CLOCK
SYNC
TYPE
TRANSMIT
FRAME SYNC
Table 9-3. Transmitter High Frequency Clock Divider
TFP3–TFP0
$0
$1
$2
$3
...
$F
SYN=0
RFSD=1
RFSD=0
SYN=1
FLAG1 IN FLAG1OUT
(SYNC MODE) (SYNC MODE)
Table 9-3 shows the specification for the divide ratio.
Divide Ratio
1
2
3
4
...
16
RFSD
FSR
TFSD
FST
Freescale Semiconductor