Freescale Semiconductor Symphony DSP56724 Reference Manual page 427

21.5.3.3.2 Bank Select Signals
Page-based interleaving allows bank signals to be multiplexed to the higher-order address pins to leave
room for future upgrades. For example, you could multiplex the bank select signals to LA[15:14], leaving
LA13 to connect to the address pin for a larger memory size.
This allows you to design a board that can be used with a current generation of SDRAM devices today,
and in the future upgrade to the next generation of SDRAM devices without requiring a new board layout.
21.5.3.3.3 SDRAM of 256 Mbit
Figure 21-54 shows a SDRAM of 256 Mbit. Note that all of the circuit diagrams mainly show the
connections, and do not guarantee signal integrity.
LSDDQM
LCS n
LSDRAS
LSDWE
LSDCAS
Local Bus
Interface
LALE
LAD[23:0]
LSDA10
LCLK
LCKE
Consider the following SDRAM organization:
• The 24-bit port size is combined with two 16-bit devices. All 16 bits of the first device and 8 bits
of the LSBs of the second device are used.
• Each device has four internal banks, 13 row address lines, and 9 column address lines.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
ADDR[14:13]
Latch
Figure 21-54. 256-Mbit SDRAM Diagram
External Memory Controller (EMC)
16M x 16-bit
SDRAM
CAS
CS
RAS
WE
BA[1:0]
DQM
CKE
CLK
ADDR[12:11,9:0]
A10
DQ[15:0]
DATA[15:0]
16M x 16-bit
SDRAM
CAS
CS
RAS
WE
BA[1:0]
DQM
CKE
CLK
ADDR[12:11,9:0]
A10
DQ[7:0]
DATA[23:16]
21-93