Freescale Semiconductor Symphony DSP56724 Reference Manual page 332

Chip Configuration Module
Table 20-16. Internal Clock Connections Between ESAI_2 and ESAI_3
EICCR:
CLOCK_NAME [1:0]
0 0 This is the default value after chip reset; there is no internal clock connection between
ESAI_3 and ESAI_2.
0 1 No internal clock connection is between ESAI_3 and ESAI_2.
1 0 ESAI_3 clock is connected with ESAI_2; ESAI_2 controls (in/out) the clock pin; the
clock signal is also input to ESAI_3 block; ESAI_3's corresponding clock pins should
be set as input.
1 1 ESAI_2 clock is connected with ESAI_3; ESAI_3 controls (in/out) the clock pin; the
clock signal is also input to ESAI_2 block; ESAI_2's corresponding clock pins should
be set as input.
The following figures show the internal clock connection between ESAI and ESAI_1 under different clock
connection control bits settings. These figures are also applicable to each of the 6 ESAI/ESAI_1 clocks.
No Internal Clock Is Connected Between ESAI and ESAI_1: 0x
An Internal Clock Is Connected Between ESAI and ESAI_1: 10
An Internal Clock Is Connected Between ESAI and ESAI_1: 11
ESAI
GPIO Port C
ESAI_1
GPIO Port E
This is the default internal clock connection for ESAI and ESAI_1. Under this setting, ESAI and
ESAI_1 clock signals are connected to their own clock pins before switching.
Figure 20-16. No Internal Clock Is Connected Between ESAI and ESAI_1: 0x
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
20-20
Table 20-17. ESAI and ESAI_1 Internal Clock Connections
Internal Clock Connection
ESAI and ESAI_1
Internal Clock Connect Control = 0x
ESAI clock signal
ESAI_1 clock signal
Description
ESAI clock signal, to pin switch
control logic with ESAI_2 block
ESAI clock signal to pin switch
control logic with ESAI_3 block
See
Figure 20-19
Figure 20-20
Figure 20-21
See
Figure 20-16
Figure 20-17
Figure 20-18
Freescale Semiconductor