Freescale Semiconductor Symphony DSP56724 Reference Manual page 146

Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
11
X:$FFFFB8
RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0
23
RHCKD RFSD RCKD RHCKP RFSP RCKP RFP3
9.2.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0)—Bits 7–0
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator.
A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at
the receiver serial bit clock (SCKR) pin of the DSP. The bit clock output is also available internally for
use as the bit clock to shift the receive shift registers. The ESAI receive clock generator functional diagram
is shown in Figure 9-3.
9.2.3.2 RCCR Receiver Prescaler Range (RPSR)—Bit 8
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used
to extend the range of the prescaler for those cases where a slower bit clock is desired. When RPSR is set,
the fixed prescaler is bypassed. When RPSR is cleared, the fixed divide-by-eight prescaler is operational
(see Figure 9-3). The maximum internally generated bit clock frequency is Fsys/4, the minimum internally
generated bit clock frequency is Fsys/(2 × 8 × 256)=Fsys/4096.
Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes
synchronization problems when using the internal DSP clock as source
(RHCKD=1 or RCKD=1).
9.2.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0)—Bits 13–9
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate
the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one
(RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000)
provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this
case.
The ESAI frame sync generator functional diagram is shown in
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
9-24
10 9 8 7
22 21 20 19
Figure 9-8. RCCR Register
NOTE
6 5 4 3
18 17 16 15
RFP2 RFP1
Figure 9-4.
2 1 0
14 13 12
RFP0 RDC4 RDC3
Freescale Semiconductor