Freescale Semiconductor Symphony DSP56724 Reference Manual page 310

Asynchronous Sample Rate Converter
{Pre_Proc,
Post_Proc}
32
{0, 1}
32
{0, 2}
44.1
{0, 2}
48
{1, 2}
64
Fsin
(kHz)
{1, 2}
88.2
{1, 2}
96
{1, 2}
128
{2, 2}
192
Comments:
In the {Pre_Proc, Post_Proc} pair, the meaning of the values {x, y}are:
Pre_Proc:
• 0 Pre-processing input path I0 as shown in
• 1 Pre-processing input path I1 as shown in
• 2 Pre-processing input path I2 as shown in
• Post_Proc:
• 0 Post-processing output path O0 as shown in
• 1 Post-processing output path O1 as shown in
• 2 Post-processing output path O2 as shown in
19.5.1.2 Miscellaneous Topics
19.5.1.2.1 Support of Physical Clocks
The device supports only physical sampling clocks. The clocks can be the clocks from SPDIF, ESAI, and
PLL.
19.5.1.2.2 Physical Clock Source Selector and Divider
The DSP program can set the Clock Source Register (ASRCSR) and Clock Divider Registers (ASRCDR1,
ASRCDR2) to choose the clock source and divide them to sample rate clock for internal use. See
Figure 19-20.
There is a restriction with the clocks: if the prescaler is set to 1, the Clock Divider can only be set to 1 and
the clock source duty cycle must be 50%.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
19-30
Table 19-22. : Pre-Processing, Post-Processing Options
44.1 48
{0, 1} {0, 1}
{0, 1} {0, 1}
{0, 2} {0, 1}
{0, 2} {0, 2}
{1, 2} {1, 2}
{1, 2} {1, 2}
{1, 2} {1, 2}
{2, 2} {2, 2}
Figure 19-19
Figure 19-19
Figure 19-19
Figure 19-19
Figure 19-19
Figure 19-19
Fsout (kHz)
64 88.2
{0, 1} {0, 1} {0, 1}
{0, 1} {0, 1} {0, 1}
{0, 1} {0, 1} {0, 1}
{0, 1} {0, 1} {0, 1}
{1, 1} {1, 1} {1, 1}
{1, 1} {1, 1} {1, 1}
{1, 1} {1, 1} {1, 1}
{2, 1} {2, 1} {2, 1}
96 128 192
{0, 0} {0, 0}
{0, 0} {0, 0}
{0, 1} {0, 0}
{0, 1} {0, 0}
{1, 1} {1, 0}
{1, 1} {1, 1}
{1, 1} {1, 1}
{2, 1} {2, 1}
Freescale Semiconductor