Freescale Semiconductor Symphony DSP56724 Reference Manual page 43

Table 2-16. Enhanced Serial Audio Interface Signals (ESAI_3) (Continued)
Signal Name Signal Type
FSR_3 Input or Output
PE1_1 Input, Output, or
Disconnected
FST_3 Input or Output
PE4_1 Input, Output, or
Disconnected
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
State during
Reset
GPIO ESAI_3's Frame Sync for Receiver
Disconnected FSR_3 is the receiver frame sync input/output signal.
In the asynchronous mode (SYN=0), the FSR_3 pin operates as the
frame sync input or output used by all the enabled receivers.
In the synchronous mode (SYN=1), the FSR_3 pin operates as either the
serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
When the FSR_3 pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR register.
When configured as the output flag OF1, the FSR_3 pin will reflect the
value of the OF1 bit in the SAICR register, and the data in the OF1 bit will
show up at the pin synchronized to the frame sync in normal mode or to
the slot in network mode.
When configured as the input flag IF1, the data value at the FSR_3 pin will
be stored in the IF1 bit in the SAISR register, synchronized by the frame
sync in normal mode or by the slot in network mode.
GPIO Port E1_1
When the ESAI_3 is configured as GPIO, PE1_1 is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
Uses an internal pull-down resistor.
GPIO ESAI_3's Frame Sync for Transmitter
Disconnected FST_3 is the transmitter frame sync input/output signal.
For synchronous mode, FST_3 is the frame sync for both transmitters and
receivers.
For asynchronous mode, FST_3 is the frame sync for the transmitters
only.
The direction is determined by the transmitter frame sync direction
(TFSD) bit in the ESAI_3 transmit clock control register (TCCR).
GPIO Port E4_1
When the ESAI_3 is configured as GPIO, PE4_1 is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
Uses an internal pull-down resistor.
Signal Descriptions
Description
2-21