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Serial Host Interface (SHI, SHI_1)
10.6.2
SPI Master Mode
Initiate SPI master mode by performing the following steps:
1. Set HEN = 1 to enable the SHI.
2
2. Set HI
C = 0 to select the SPI mode.
3. Set HMST = 1 to select the master mode of operation.
Before enabling the SHI as an SPI master device, the programmer should program the proper clock rate,
phase and polarity in the HCKR register. When configured in the SPI master mode, the SHI external pins
operate as follows:
•
SCK/SCL is the SCK serial clock output.
•
MISO/SDA is the MISO serial data input.
•
MOSI/HA0 is the MOSI serial data output.
•
SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
•
HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a GPIO pin
connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted
(high) for proper operation. If the SPI master device's SS pin is asserted, the host bus error status bit
(HBER) is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service
the SHI bus error interrupt.
In the SPI master mode, the DSP must write to the HTX register to receive, transmit or perform a
full-duplex data transfer. Actually, the interface performs simultaneous data receive and transmit. The
status bits of both receive and transmit paths are active; however, the programmer may disable undesired
interrupts and ignore irrelevant status bits. In a data transfer, the HTX register is transferred to the IOSR
register, clock pulses are generated, the IOSR register data is shifted out (via MOSI) and received data is
shifted in (via MISO). The DSP programmer may write the HTX register (if the HTDE status bit is set)
using either DSP instructions or DMA transfers to initiate the transfer of the next word. The HRX FIFO
contains valid receive data, which the DSP can read using either DSP instructions or DMA transfers, if the
HRNE status bit is set.
It is recommended that an SHI individual reset (HEN bit is cleared) be generated before beginning data
reception to reset the receive FIFO to its initial (empty) state (for example, when switching from
transmitting to receiving data).
If the HRQE[1:0] bits are cleared, the HREQ input pin is ignored by the SPI master device; if any of the
the HRQE[1:0] bits are set, the HREQ input pin is considered by the SPI master device.
When asserted by the slave device, the HREQ input pin indicates that the external slave device is ready
for the next data transfer. As a result, the SPI master sends clock pulses for the full data word transfer. At
the first clock pulse of the new data transfer, the external slave device deasserts HREQ. When HREQ is
deasserted, HREQ prevents the clock generation of the next data word transfer until HREQ is asserted
again.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
10-22
Freescale Semiconductor
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