Freescale Semiconductor Symphony DSP56724 Reference Manual page 56

Memory Map
Legend for the following tables:
peripheral.
Address Range
X: $FF_FFFF–$FF_FFFD
X: $FF_FFFC
X: $FF_FFFB–$FF_FFF9
X: $FF_FFF8–$FF_FFF5
X: $FF_FFF4–$FF_FFD0
X: $FF_FFBF–$FF_FFA0
X: $FF_FF9A–$FF_FF98
X: $FF_FF97–$FF_FF90
X: $FF_FF8F–$FF_FF80
X: $FF_FF7F–$FF_FF7C
X: $FF_FF7B–$FF_FF78
X: $FF_FF77–$FF_FF60
X: $FF_FF5F–$FF_FE6C
X: $FF_FE6B–$FF_FE00
X: $FF_FDFF–$FF_E000
Address Range
Y: $FF_FFFF–$FF_FFF8
Y: $FF_FFF7–$FF_FFF0
Y: $FF_FFEF–$FF_FFE8
Y: $FF_FFE7–$FF_FFE0
Y: $FF_FFDF–$FF_FFDC
Y:$FF_FFDB–$FF_FFD0
Y: $FF_FFCF–$FF_FFCB
Y: $FF_FFCA
Y: $FF_FFC9
Y: $FF_FFC8
Y: $FF_FFC8–$FF_FFC4
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
3-4
Yellow indicates a dedicated peripheral, while
Table 3-5. X-Memory Map for DSP Core-0 and Core-1
DMA Control and DMA channels
ESAI, GPIO PORT C
Triple Timer (TEC)
Table 3-6. Y-Memory Map for DSP Core-0 and Core-1
ESAI/ESIA_1 internal clock control
EMC/ICC Error Status Register
Blocks
DSP Core-0
PIC
CIM
PIC
CIM
GPIO port H
SHI
CGM
Reserved
S/PDIF
Reserved
EMC
Reserved
Blocks
DSP Core-0
GPIO Port G
GPIO Port A
Reserved
Chip Configuration Registers
Reserved
ICC
Reserved
Reserved
Reserved
blue indicates a shared
DSP Core-1
PIC_1
CIM_1
PIC_1
CIM_1
DMA_1 Control and DMA_1 channels
ESAI_2, GPIO PORT C1
GPIO port H
SHI_1
Triple Timer (TEC_1)
DSP Core-1
Reserved
ICC
Reserved
ESAI_2/ESIA_3 internal clock control
Reserved
EMC/ICC Error Status Register
Reserved
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