Inter-Core Non-Maskable Interrupts - Freescale Semiconductor Symphony DSP56724 Reference Manual

Inter-Core Communication (ICC)
other core. When the other core services this interrupt, it reads its own read-only communication data
register (ICDR4) to obtain the data from the core that produces the interrupt. This reading operation will
clear the IF bit and set the ACK bit of the other core's ICAR3 register, and an acknowledge interrupt is
generated to indicate the serviced core that the interrupt has been serviced. The ACK bit can be cleared by
writing 1 to the RACK bit of ICAR3 register.
For the core that generates the interrupt, the IE bit is readable and writable, but the IF bit is read-only. For
the core that services the interrupt, IF and IE are read-only register bits.
For the core that generates the maskable interrupt, the RACK bit is read-writable and the ACK bit is
read-only. For the core that services the maskable interrupt, RACK and ACK are both read-only bits.
13.3.2

Inter-Core Non-Maskable Interrupts

The ICC non-maskable interrupt operation is shown in
One Core
writes
DRE == 1
Note: IF bit is
cleared
automatically by
hardware.
When one DSP core needs to generate a non-maskable interrupt to the other core, that core writes a datum
to the ICDR1 data register. However, the data can be written to this register and the IF bit can only be set
when DRE is 1, which indicates that the data register is empty. So the DRE bit must be polled before
writing a datum to the ICDR1 data register. When the core writes a datum successfully into the ICDR1
register, the DRE bit is cleared to indicate that the ICDR1 register is full, and the other core can now read
this data correctly using its interrupt service routine. After the other core has read the communication data
via its read-only ICDR2 register, the DRE bit will be set to indicate that the ICDR1 register is empty again.
The IF bit of the inter-core non-maskable interrupt control register (ICCR1) is not cleared by writing 1 to
it or by the other core's reading of the ICDR1 register. The IF bit of the ICCR1 register is automatically
cleared by the hardware when the other core has serviced this non-maskable interrupt.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
13-14
ICDR1
Set IF bit
Clear
DRE
DRE
ICCR1
Figure 13-16. Non-Maskable Interrupts
Figure 13-16.
IF
Set DRE
Other Core
reads
DRE == 0
NMI to the
other Core
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