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Watchdog Timer (WDT, WDT_1)
12.4
Watchdog Operating Modes
12.4.1
Wait Mode
If the WCR[3] bit is set, then the Watchdog timer function stops and enters Wait mode. The counter and
the prescaler retain their values during Wait mode. If the WCR[3] bit is cleared, the timer function is
unaffected in Wait mode. All register accesses function in the normal fashion, regardless of the value of
the WCR[3] bit.
12.4.2
Debug Mode
If the WCR[1] bit is set, the Watchdog timer function stops and enters Debug mode. The counter and the
prescaler retain their values during Debug mode. If the WCR[1] bit is cleared, the timer function is
unaffected in Debug mode. In Debug mode, the WMR and WCR registers can be updated like a simple
read/write register. The write-once property of these registers do not apply in Debug mode. All changes
made in Debug mode are retained. A write-once register bit that has not previously been written is still
writable when Debug mode is exited.
12.4.3
Stop Mode
The Fsys is assumed to be stopped in Stop mode. The watchdog timer does not function in Stop mode.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
12-6
Freescale Semiconductor
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