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Memory Map
On-chip peripherals are connected to the core using the peripheral bus or Shared Peripheral bus. The
on-chip peripherals use the addresses above $FFF000 (including $FFF000).
3.2
Data and Program Memory Maps
The on-chip memory configuration for each DSP is affected by the state of the memory switch control bits
in the Operating Mode Register (OMR). These bits are the Master Memory Switch Mode (MS) bit, the
Memory Switch Mode 0 (MSW0) bit, and the Memory Switch Mode 1 (MSW1) bit.
MSW1
—
0
0
1
1
MSW1
—
0
0
1
1
Configuration
MSW = NA, MS = 0
MSW1 = 1, MSW0 = 1, MS = 1
MSW1 = 1, MSW0 = 0, MS = 1
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
3-2
Table 3-1. Core-0 Configuration
Bit Settings
MSW0
—
0
1
0
1
Table 3-2. Core-1 Configuration
Bit Settings
MSW0
—
0
1
0
1
Table 3-3. DSP Core-0 Memory Map Locations
$000000 – $000FFF
$000000 – $001FFF
$000000 – $003FFF
MS
Program RAM
0
4 K
1
40 K
1
24 K
1
16 K
1
8 K
MS
Program RAM
0
2 K
1
16 K
1
12 K
1
8 K
1
4 K
Program RAM
4 K
1 × 4 K block
$000000 – $006FFF
8 K
$000000 – $005FFF
16 K
$000000 – $005FFF
Memory Space
X Data RAM
28 K
8 K
16 K
24 K
24 K
Memory Space
X Data RAM
12 K
4 K
8 K
8 K
12 K
X Data RAM
Y Data RAM
28 K
1 × 4 K block
3 × 8 K block
3 × 8 K block
$000000 – $005FFF
24 K
$000000 – $005FFF
24 K
$000000 – $003FFF
Freescale Semiconductor
Y Data RAM
24 K
8 K
16 K
16 K
24 K
Y Data RAM
10 K
4 K
4 K
8 K
8 K
24 K
24 K
16 K
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