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Inter-Core Communication (ICC)
error), there is a read-only status register implemented, called the Error Interrupt Status Register. The
address of this read-only status register is
Address
Y:FFFFC8
23
22
R
W
Reset
0
11
10
R
W
Reset
0
Each core has an EISR register. For Core-0's EISR register, the IEF indicates the flag of the error interrupt
to Core-0. For Core-1's EISR register, the IEF bit indicates the flag of the error interrupt to Core-1.
To see which module produces this error interrupt, you must poll this ESIR register in the interrupt service
routine. If the interrupt is caused by the ICC, then write a one (1) to the ICCR3[2] bit to clear this status
flag.
13.3.5
Reset
Both hardware reset and software reset can put all of the ICC registers to a known state.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
13-16
Y:$FFFFC8.
21
20
0
0
0
9
8
0
0
0
Figure 13-19. Error Interrupt Status Register (EISR)
Table 13-15. EISR Field Description
Bit
Field
23–2
Reserved
1
LEF
EMC Error Flag
1: EMC Error is Generated
0: EMC Error is Not Generated
0
IEF
ICC Error Flag
1: ICC Error Condition is Generated
0: ICC Error Condition is Not Generated
See
Figure 13-19
19
18
17
0
0
0
7
6
5
0
0
0
Description
for the bit definitions.
Access: User Read
16
15
14
0
0
0
4
3
2
0
0
0
Freescale Semiconductor
13
12
0
0
1
0
LEF
IEF
0
0
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