Freescale Semiconductor Symphony DSP56724 Reference Manual page 231

Bit Field
2 EF Error Flag.
1: Error Generated
0: No Error Generated
This error status bit can be read, and is cleared by writing a one (1).
1 MIF Local Interrupt Flag for Maskable Interrupt
1: Flag set, indicates that an interrupt condition occurs.
0: Flag cleared, no interrupt condition occurs.
0 MIE Local Interrupt Enable bit for Maskable Interrupt
1: Interrupt Enabled, the maskable interrupt will be generated to the other core when the interrupt
condition occurs.
0: Interrupt Disabled. No interrupt will be generated even if the interrupt condition occurs.
13.2.2.7 ICAR3 (ICC Acknowledge Register 3)
The ICAR3 Control Register is shown in
Address Y:FFFFD5
23 22
R
W
Reset 0
11 10
R
W
Reset 0
Bit Field
23–2 Reserved Write 0 for future compatibility.
1 RACK Reset ACK bit of this register. Writing a one (1) to this bit will clear the ACK bit.
0 ACK Maskable interrupt acknowledge bit.
1: Asserted when the other core has serviced the maskable interrupt.
0: No interrupt serviced has been by the other core. To clear ACK bit, write a one (1) to RACK bit (which
means that the ACK interrupt is serviced).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 13-8. ICCR3 Field Descriptions (Continued)
Figure
21 20
0 0 0
9 8
0 0 0
Figure 13-9. ICC ICAR3 Control Register
Table 13-9. ICAR3 Field Descriptions
Description
13-9.
19 18 17
0 0 0
7 6 5
0 0 0
Description
Inter-Core Communication (ICC)
Access: User Read/Write
16 15 14
0 0 0
4 3 2
RACK
0 0 0
13 12
0 0
1 0
ACK
0 0
13-9