Register Descriptions - Freescale Semiconductor Symphony DSP56724 Reference Manual

Address Offset
0xFF_FE53
0xFF_FE54
–
0xFF_FE57
0xFF_FE58
0xFF_FE59
0xFF_FE5A
0xFF_FE5B
0xFF_FE5C
0xFF_FE5D
0xFF_FE5E
0xFF_FE5F
0xFF_FE60
0xFF_FE61
0xFF_FE62
–
0xFF_FE67
0xFF_FE68
0xFF_FE69
0xFF_FE6A
0xFF_FE6B
21.3.2

Register Descriptions

This section provides a detailed description of the EMC configuration, status, and control registers, with
detailed bit and field descriptions.
Address offsets in the EMC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 21-3. EMC Registers Memory Map (Continued)
Register
SRT SDRAM refresh timer
Reserved
Reserved. Transfer error status register has
no low part.
TESR Transfer error status register
Reserved. Transfer error disable register
has no low part.
TEDR Transfer error disable register
Reserved. Transfer error interrupt register
has no low part.
TEIR Transfer error interrupt register
TEATRL Transfer error attributes register low part
TEATRH Transfer error attributes register high part
TEARL Transfer error address register low part
TEARH Transfer error address register high part
Reserved
BCRL Configuration register low part
BCRH Configuration register high part
CRRL Clock ratio register low part
CRRH Clock ratio register high part
External Memory Controller (EMC)
Access Reset Value
R/W 0x00_0000
Read/ 0x00_0000
Write Clear
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0000
R/W 0x00_0008
R/W 0x00_8000
Table 21-3 should not be accessed for
21-9