Freescale Semiconductor Symphony DSP56724 Reference Manual page 412

External Memory Controller (EMC)
• LAST and REDO must not be set together.
• REDO should not be used within the exception routine.
21.4.4.4.6 Address Multiplexing (AMX)
The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex
bits can choose between driving the transaction address, driving it according to the multiplexing specified
by the MxMR[AM] field, or driving the MAR contents on the address signals. In all cases, the LA[2:0]
signals of the EMC are driven by the 3 LSBs of the address selected by AMX, regardless of whether the
NA bit of the RAM word is used to increment the current address. The effect of NA = 1 is visible only
when AMX = 00 chooses the column address.
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the LAD[23:0] bus with the assertion of LALE for the number of cycles set for LALE in
the ORx and CRR registers. The LGPL[5:0] signals maintain the value specified in the RAM word during
the LALE phase.
21.4.4.4.7 Data Valid and Data Sample Control (UTA)
When a read access is handled by the UPM, and the UTA bit = 1 (data is to be sampled by EMC), the value
of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPLx4DIS], determines when the
data input is sampled by EMC, as follows:
• If MxMR[GPLx4DIS] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data
is latched on the falling edge of the bus clock instead of the rising edge. The data is sampled by
EMC on the next falling edge of the bus clock, which is during the middle of the current bus cycle.
This feature should only be used in systems without external synchronous bus devices that require
mid-cycle sampling.
• If MxMR[GPLx4DIS] = 0 (G4T4/DLT3 functions as G4T4), or if MxMR[GPLx4DIS] = 1 but
DLT3 = 0, data is latched on the rising edge of the bus clock, which occurs at the end of the current
bus clock cycle (normal operation).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-78 Freescale Semiconductor