Freescale Semiconductor Symphony DSP56724 Reference Manual page 294

Asynchronous Sample Rate Converter
Table 19-8. Filter Configuration Status Register (ASRCFG) (Continued)
Bit Field
11–10 PREMODB Pre-Processing Configuration for Conversion Pair B
[1-0] Use these bits to set the selection of the post-processing configuration for Pair B.
00 Select Upsampling-by-2, as defined in
01 Select Direct-Connection, as defined in
10 Select Downsampling-by-2, as defined in
11 Select passthrough mode. In this case, POSTMODB[1-0] will not apply.
These bits can be read/written by the user if ASRCTR:ATSB = 0, and can also be automatically updated
by the ASRC internal logic if ASRCTR:ATSB = 1 (see
9–8 POSTMODA Post-Processing Configuration for Conversion Pair A
[1-0] Use these bits to set the selection of the post-processing configuration for Pair A.
00 Select Upsampling-by-2, as defined in
01 Select Direct-Connection, as defined in
10 Select Downsampling-by-2, as defined in
These bits can be read/written by the user if ASRCTR:ATSA = 0, and can also be automatically updated
by the ASRC internal logic if ASRCTR:ATSA = 1 (see
7–6 PREMODA Pre-Processing Configuration for Conversion Pair A
[1-0] Use these bits to set the selection of the post-processing configuration for Pair A.
00 Select Upsampling-by-2, as defined in
01 Select Direct-Connection, as defined in
10 Select Downsampling-by-2, as defined in
11 Select passthrough mode. In this case, POSTMODA[1-0] will not apply.
These bits can be read/written by the user if ASRCTR:ATSA = 0, and can also be automatically updated
by the ASRC internal logic if ASRCTR:ATSA = 1 (see
pre-processing configuration.
5–0 Reserved. Should be written as zero for compatibility.
19.2.2.5 ASRC Clock Source Register (ASRCSR)
The clock source register (ASRCSR) is a 24-bit read/write register that controls the sources of the input
and output clocks of the ASRC.
Offset 0x5
23 22
R
W
Reset 0
11 10
R
W
Reset 0
The bit definitions are in
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
19-14
21 20
AOCSC
0 0 0
9 8
AICSC
0 0 0
Figure 19-9. Clock Source Register (ASRCSR)
Table 19-9.
Description
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Table
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Table
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Section 19.5.1.1, "Signal Processing Flow."
Table
19 18 17
AOCSB
0 0 0
7 6 5
AICSB
0 0 0
19-4).
19-4).
19-4). These bits set the selection of the
Access: User Read/Write
16 15 14
AOCSA
0 0 0
4 3 2
AICSA
0 0 0
Freescale Semiconductor
13 12
0 0
1 0
0 0