Freescale Semiconductor Symphony DSP56724 Reference Manual page 408

External Memory Controller (EMC)
Bits Name
21–20 G0H General purpose line 0 higher.
Defines the state of LGPL0 during the bus clock quarter phases 3 and 4 (second half phase).
00 Value defined by MxMR[G0CL]
01 Reserved
10 0
11 1
19 G1T1 General purpose line 1 timing 1.
Defines the state (0 or 1) of LGPL1 during bus clock quarter phases 1 and 2 (first half phase).
18 G1T3 General purpose line 1 timing 3.
Defines the state (0 or 1) of LGPL1 during bus clock quarter phases 3 and 4 (second half phase)
17 G2T1 General purpose line 2 timing 1.
Defines state (0 or 1) of LGPL2 during bus clock quarter phases 1 and 2 (first half phase).
16 G2T3 General purpose line 2 timing 3.
Defines the state (0 or 1) of LGPL2 during bus clock quarter phases 3 and 4 (second half phase).
15 G3T1 General purpose line 3 timing 1.
Defines the state (0 or 1) of LGPL3 during bus clock quarter phases 1 and 2 (first half phase).
14 G3T3 General purpose line 3 timing 3.
Defines the state (0 or 1) of LGPL3 during bus clock quarter phases 3 and 4 (second half phase).
13 G4T1/DLT3 General purpose line 4 timing 1/delay time 3. The function of this bit is determined by MxMR[GPL4].
If MxMR[GPL4] = 0 and LGPL4/UPWAIT pin functions as an output (LGPL4), then G4T1/DLT3 defines
the state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).
If MxMR[GPL4] = 1 and LGPL4/UPWAIT functions as an input (UPWAIT), and if a read burst or single
read is executed, then G4T1/DLT3 defines the sampling of the data bus as follows:
0 In the current word, the data bus should be sampled at the start of bus clock quarter phase 1 of the
next bus clock cycle.
1 In the current word, the data bus should be sampled at the start of bus clock quarter phase 3 of the
current bus clock cycle.
12 G4T3/WAEN General purpose line 4 timing 3/wait enable. The function of this bit is determined by MxMR[GPL4].
If MxMR[GPL4] = 0 and LGPL4/UPWAIT pin functions as an output (LGPL4), then G4T3/WAEN defines
the state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).
If MxMR[GPL4] = 1 and LGPL4/UPWAIT functions as an input (UPWAIT), then G4T3/WAEN is used to
enable the wait mechanism:
0 UPWAIT detection is disabled.
1 UPWAIT is enabled. If UPWAIT is detected as being asserted, a freeze in the external signals logical
values occurs until UPWAIT is detected as being negated.
11 G5T1 General purpose line 5 timing 1.
Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 1 and 2 (first half phase).
10 G5T3 General purpose line 5 timing 3.
Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 3 and 4 (second half phase).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
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Table 21-72. RAM Word Field Descriptions (Continued)
Description
Freescale Semiconductor