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EMC Burst Buffer
17.3.2.2
Burst Read
There are two burst read buffers: one burst read buffer for Shared Bus master 0, and one burst read buffer
for Shared Bus master 1. Each Shared Bus master uses its own read buffer independently.
Each read buffer has 16 24-bit words alternating (ping-pong style operation) between the two sets of 8
words, and there are two 8-word buffers in each read buffer.
The burst read is always an 8-beat transfer to the EMC.
In one read buffer, each 8-word buffer has a 26-bit base address register, because the Shared Bus access
address is 26-bits— actually consists of a 24-bit address and a 2-bit encoded address space.
Each 8-word buffer has one "valid" bit, which indicates that the read data in the 8-word read buffer is
available for burst read access when the bit asserted.
During an burst read access, the module compares the access address with the base address register for the
two 8-word buffers, respectively.
•
If the address is inside the range from base address to (base address + 7) in either 8-word buffer,
the data is in the buffer, and the buffer returns the read data to the Shared Bus directly with zero
wait states.
•
If no 8-word buffer is hit, the module sends an 8 word burst request to the EMC to load 8 words
from external memory into the first 8-word buffer; at the same time, the access address is loaded
into the base address register. After the burst operation has finished, the corresponding "valid" bit
is set, and the read data that was loaded into the buffer is returned.
•
If the data hit is the first time for one 8-word buffer (after the last burst operation has finished), or
is the first data hit for one of the 8 word buffers, then the module triggers the other 8-word buffer
to execute an 8-word burst operation after the end address of the last burst operation, and on the
following 8 words in external memory, the module stores the burst access address into the base
address register. The two 8-word buffers alternately execute bursts (ping-pong style).
When an 8-word buffer is executing a burst operation, the other 8-word buffer can return its data (stored
in it) to the Shared Bus on a hit due to a read access.
17.3.3
Write Access
When the current access is a write access inside the available burst address scope, the EMC Burst Buffer
executes a burst write operation; otherwise the access is taken as a single write access.
The
Figure 17-3
shows the write transfer.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
17-6
Freescale Semiconductor
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