Freescale Semiconductor Symphony DSP56724 Reference Manual page 147

9.2.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0)—Bits 17–14
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit
clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock.
When the HCKR input is being driven from an external high frequency clock, the RFP3–RFP0 bits specify
an additional division ration in the clock divider chain.
ratio. Figure 9-3 shows the ESAI high frequency generator functional diagram.
9.2.3.5 RCCR Receiver Clock Polarity (RCKP)—Bit 18
The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked
out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the
receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is
set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of
the receive clock is used to latch the frame sync in.
9.2.3.6 RCCR Receiver Frame Sync Polarity (RFSP)—Bit 19
The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When
RFSP is cleared the frame sync signal polarity is positive, that is, the frame start is indicated by a high level
on the frame sync pin. When RFSP is set the frame sync signal polarity is negative, that is, the frame start
is indicated by a low level on the frame sync pin.
9.2.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP)—Bit 20
The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and
frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked
out on the rising edge of the receive high frequency bit clock and the frame sync is latched in on the falling
edge of the receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data
and frame sync out and the rising edge of the receive clock is used to latch the frame sync in.
9.2.3.8 RCCR Receiver Clock Source Direction (RCKD)—Bit 21
The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the
receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the
synchronous mode (SYN=1).
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
Table 9-6. Receiver High Frequency Clock Divider
RFP3–RFP0
$0
$1
$2
$3
...
$F
Table 9-6 provides the specification of the divide
Divide Ratio
1
2
3
4
...
16
9-25